preliminary very low jitter field and factory programmable clock generator cy22180 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-15577 rev. ** revised may 10, 2007 features ? low period and cycle-to-cycle jitter ? typical pk-pk period jitter: 60 ps ? wide output frequency range ? commercial temperature: 20?200 mhz ? industrial temperature: 20?166 mhz ? input frequency range ? external crystal: 10?30 mhz fundamental crystal ? external reference: 10?133 mhz clock ? integrated phase-locked loop (pll) ? field programmable and factory programmed options ? programmable crystal load capacitor tuning array ? 3.3v operation ? commercial and industrial temperature ranges ? power down or output enable function benefits ? internal pll generates up to 200 mhz output. can generate custom frequencies from an external crystal or a driven source. ? in-house programming of samples and prototype quantities can be done using the cy3672-usb programmer and cy3619 socket adapter. production quantities are available through cypress?s value added distribution partners or by using third party programmers from bp microsystems, hilo systems, and others. ? eliminates the need for expensive and difficult to use higher-order crystals. ? enables fine-tuning of output clock frequency by adjusting c load of the crystal. eliminates the need for external c load capacitors. ? application compatibility in standard and low-power systems ? enables low-power state or output clocks to high-z state. logic block diagram pin configuration cy22180 8-pin soic 4 8 xin/clkin 6 7 refout clkout xout 1 2 3 vdd pd#/oe vss nc 5 pll programmable configuration output divider 1 8 3 2 4 5 6 vdd vss clkout refout xout xin/clkin pd# or oe c xout c xin
preliminary cy22180 document #: 001-15577 rev. ** page 2 of 8 general description the cy22180 is a low jitter clock generator for use in networking, telecommunication, datacom, consumer electronics, and other general purpose applications. the cy22180 offers a single programmable output and an optional copy of the input frequency. the on-chip reference oscillator is designed to run off a 10?30 mhz crystal, or a 10?133 mhz external clock signal. the output frequency range is 20?200 mhz. the cy22180 comes in an 8-pin soic, and requires a 3.3v power supply. programming description field programmable (cy22180fsxc and cy22180fsxi) the cy22180 is programmed at the package level, that is, in a programmer socket. the cy22180 is flash technology based, so the parts can be reprogrammed up to 100 times. this enables fast and easy design changes and product updates, and eliminates any issu es with old and out-of-date inventory. samples and small prototype quantities can be programmed on the cy3672 programmer with the cy3619 socket adapter. cyberclocks ? online software cyberclocks online software is a web-based software appli- cation that allows the user to custom-configure the cy22180. all the parameters in table 1 given as ?enter data? can be programmed into the cy22180. cyberclocks online outputs an industry-standard jedec file used for programming the cy22180. cyberclocks online is available at www.cyberclocksonline.com through user registration. for more information on the registration process refer to the cy3672 data sheet. cy3672-usb programming kit and cy3619 socket adapter the cypress cy3672 ftg programmer and cy3619 socket adapter are needed to program the cy22180. the socket adapter comes with small prototype quantities of cy22180. the cy3619 can be ordered separately, so existing users of the cy3672-usb programmer need order only the socket adapters to program the cy22180. factory programmed cy22180 factory programming is available for volume manufacturing by cypress. all requests must be submitted to the local cypress field application engineer (fae) or sales representative. once the request has been processed, you will receive a new part number (dash number) and samples with the programmed values. this part number will be used for additional sample requests and production orders. additional information on the cy22180 can be obtained from the cypress website at www.cypress.com . pin description pin name description 1 xin/clkin crystal input or reference clock input. 2 vdd 3.3v power supply. 3 pd#/oe power down pin, active low. if pd# = 0, the pll and oscillator are powered down and outputs are weakly pulled low. output enable pin, active high. if oe = 1, clkout and refout are enabled. user has the option of choosi ng either pd# or oe function. 4 vss power supply ground. 5 refout buffered reference output. 6 clkout low jitter clock output. 7 nc no connect. leave this pin floating. 8 xout crystal output. leave this pin floating if external clock is used. table 1. pin function input frequency total xtal load capacitance output frequency reference output power-down or output enable pin name xin and xout xin and xout clkout refout pd#/oe pin# 1 and 8 1 and 8 6 5 3 unit mhz pf mhz on or off select pd# or oe program value enter data enter data enter data enter data enter data
preliminary cy22180 document #: 001-15577 rev. ** page 3 of 8 product functions input frequency (xin, pin 1 and xout, pin 8) the input to the cy22180 can be a crystal or a clock. the input frequency range for crystals is 10 to 30 mhz, and for clock signals is 10 to 133 mhz. c xin and c xout (pin 1 and pin 8) the internal load capacitors at pin 1 (c xin ) and pin 8 (c xout ) can be programmed from 12 pf to 60 pf in 0.5-pf increments. thus, these programmable capacitors support crystals with c l values between 6 pf and 30 pf. the crystal c l value, minus board parasitic capacitance, is the value entered into cyber- clocks online software. if using a driven reference, cyberclocks online software will set c xin and c xout to the minimum value 12 pf. output clock (clkout, pin 6) the output clock can be programmed to any frequency in the range of 20?200 mhz. reference output (refout, pin 5) the reference clock output has the same frequency as the input clock. this output can be programmed to be enabled (clock on) or disabled (high-z, clock off) through cyberclocks online software. if this output is not needed, cypress recom- mends that users request the disabled (high-z, clock off) option. power down or output enable (pd# or oe, pin 3) the cy22180 can be programmed to include either pd# or oe function. pd# function can be used to power down the oscil- lator and pll. the oe function disables the outputs but does not turn off the pll. pd# achieves lower power consumption, but pll start up time means that turn-on time is slower than for oe. absolute maximum ratings supply voltage (v dd ) ........................................?0.5 to +7.0v dc input voltage...................................... ?0.5v to v dd + 0.5 storage temperature (non-condensing)..... ?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention @ tj = 125 c................................> 10 years package power dissipation...................................... 350 mw static discharge voltage.......................................... > 2000v (per mil-std-883, method 3015) recommended crystal specifications parameter description comments min. typ. max. unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 10 ? 30 mhz c lnom nominal load capacitance 6 ? 30 pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 dl crystal drive level no external series resistor assumed ? 0.5 2 mw operating conditions parameter description min. typ. max. unit v dd supply voltage 3.13 3.30 3.45 v t a ambient commercial temperature 0 ? 70 c ambient industrial temperature ?40 ? 85 c c load max. load capacitance @ pin 5 and pin 6 ? ? 10 pf f xin external reference crystal 10 ? 30 mhz f clkin external reference clock 10 ? 133 mhz f clkout clkout frequency, commercial temperature 20 ? 200 mhz clkout frequency, industri al temperature 20 ? 166 mhz f refout refout frequency 10 ? 133 mhz t pu power-up time for all v dd s to reach minimum specified voltage (power ramp must be monotonic) 0.05 ? 500 ms
preliminary cy22180 document #: 001-15577 rev. ** page 4 of 8 l dc electrical characteristics parameter description condition min typ max unit i oh output high current v oh = v dd ? 0.5v, v dd = 3.3v (source) 10 12 ma i ol output low current v ol = 0.5v, v dd = 3.3v (sink) 10 12 ma v ih input high voltage cmos levels, 70% of v dd 0.7v dd ?v dd + 0.3 v v il input low voltage cmos levels, 30% of v dd ?0.3 ? 0.3v dd v i ih input high curr ent, pd#/oe v in = v dd ?? 10 a i il input low current, pd#/oe v in = v ss , pull up disabled ? ? 10 a v in = v ss , pull up enabled ? ? 55 a i oz output leakage current three-state output, pd#/oe = 0 ?10 10 a c xin or c xout [1] programmable capacitance at pin 1 and pin 8 capacitance at minimum setting ? 12 ? pf capacitance at maximum setting ? 60 ? pf c in [1] input capacitance at pd#/oe ?5 7pf i dd supply current f in = 10 mhz, f out = 33 mhz, refout off ? 11 15 ma i dds standby current device powered down with pd# = 0v (driven reference pulled down) ?10 40 a ac electrical characteristics [1] parameter description condition min typ max unit dc output duty cycle clkout < 125 mhz, measured at v dd /2 45 50 55 % output duty cycle clkout > 125 mhz, measured at v dd /2 40 50 60 % output duty cycle refout, measured at v dd /2 duty cycle of clkin = 50% 45 50 55 % sr1 rising edge slew rate clkout from 20 to 200 mhz; refout from 10 to 133 mhz. 20%?80% of v dd 23 ?v/ns sr2 falling edge slew rate clkout from 20 to 200 mhz; refout from 10 to 133 mhz. 80%?20% of v dd 23 ?v/ns t pj1 [2, 3] clkout pk-pk period jitter, refout off clkout = 20?200 mhz ? ? 75 (38) ps t pj2 [2, 3] clkout pk-pk period jitter, refout off, specific frequencies clkin = 10 mhz, clkout = 20, 33, 66, 80, 106.25, 125, 133, or 200 mhz ?? 60 (30) ps clkin = 25 mhz, clkout = 125 mhz ? ? 56 (28) ps clkin = 30 mhz, clkout = 33, 66, 80, 106.25, 125, or 133 mhz ?? 62 (31) ps clkin = 66 mhz, clkout = 33 or 66 mhz ? ? 47 (24) ps clkin = 66 mhz, clkout = 80, 106.25, 125, 133, 166, or 200 mhz ?? 68 (34) ps clkin = 133 mhz, clkout = 33, 66, or 80 mhz ? ? 68 (34) ps clkin = 133 mhz, clkout = 125, 133, or 166 mhz ?? 52 (26) ps notes 1. guaranteed by characterization, not 100% tested. 2. jitter is configuration dependent. actual jitter is dependent on xin jitter and edge rate, number of active outputs, output f requencies, temperature, and output load. for more information, refer to the application note, ?jitter in pll based systems: causes, effects, and solutions?. 3. cycle-to-cycle jitter (peak) is always less than period jitter (peak-to-peak). peak-to-peak pe riod jitter is the difference b etween the shortest and longest measured periods.
preliminary cy22180 document #: 001-15577 rev. ** page 5 of 8 t pj3 [2, 3] clkout pk-pk period jitter, refout on clkout = 20?200 mhz ? 150 (75) ?ps t pj4 [2, 3] refout pk-pk period jitter refout = 10-133 mhz ? ? 265 (133) ps t stp power down time (pin 3 = pd#) time from falling edge on pd# to stopped outputs (asynchronous) ? 150 350 ns t oe1 output disable time (pin 3 = oe) time from falling edge on oe to stopped outputs (asynchronous) ? 150 350 ns t oe2 output enable time (pin 3 = oe) time from rising edge on oe to outputs at a valid frequency (asynchronous) ? 150 350 ns t pu1 power up time, crystal is used time from rising edge on pd# to outputs at valid frequency (asynchronous) ?3.5 5 ms t pu2 power up time, reference clock is used time from rising edge on pd# to outputs at valid frequency (asynchronous), reference clock at correct frequency ?2 3ms ac electrical characteristics [1] parameter description condition min typ max unit notes 4. since the load capacitors (c xin and c xout ) are provided by the cy 22180, no external capacit ors are needed on the xin and xout pins to match the crystal load capacitor (c l ). only a single 0.1- f bypass capacitor is required on the v dd pin. 5. if an external clock is used, apply the clock to xin (pin 1) and leave xout (pin 8) floating (unconnected). application circuits [4, 5] 0.1uf vdd or control 1 3 2 4 5 6 7 8 xin/clkin vdd pd#/oe vss refout clkout nc xout power cy22180 crystal no connect 0.1uf 1 3 2 4 5 6 7 8 xin/clkin vdd pd#/oe vss refout clkout nc xout power cy22180 clkin no connect no connect vdd or control
preliminary cy22180 document #: 001-15577 rev. ** page 6 of 8 switching waveforms figure 1. duty cycle timing (dc = t 1a /t 1b ) figure 2. output rise/fa ll time (clkout and refout) figure 3. power down timing and power up timing figure 4. output enable/disable timing t 1a t 1b output output tr v dd 0v tf output rise time (tr) = (0.6 x v dd )/sr1 (or sr3) output fall time (tf) = (0.6 x v dd )/sr2 (or sr4) refer to ac electrical characterist ics table for sr (slew rate) values. clkout v dd t pu t stp v il v ih power down 0v (asynchronous ) high impedance clkout v dd t oe1 v il v ih output enable 0v (asynchronous ) high impedance t oe2
preliminary cy22180 document #: 001-15577 rev. ** page 7 of 8 cyberclocks is a trademark of cypress semiconductor. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. ordering information part number [6] description product flow cy22180fsxc field programmable, pb-free commercial, 0 to 70c cy22180fsxi field programmable, pb-free industrial, ?40 to 85c CY22180SXC-XXX factory programmed, pb-free commercial, 0 to 70c CY22180SXC-XXXt factory progra mmed, tape and reel - pb-f ree commercial, 0 to 70c cy22180sxi-xxx factory programmed, pb-free industrial, ?40 to 85c cy22180sxi-xxxt factory programmed, tape and reel - pb-free industrial, ?40 to 85c cy3672-usb ftg programmer n/a cy3619 cy22180fsxc and cy22180fsxi socket adapter n/a note 6. ?xxx? denotes the assigned product dash num ber for devices that are factory-programmed. package diagrams figure 5. 8-lead (150-mil) soic s8 seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c
preliminary cy22180 document #: 001-15577 rev. ** page 8 of 8 ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. document history page document title: cy22180 very low jitter field and factory programmable clock generator document number: 001-15577 rev. ecn no. issue date orig. of change description of change ** 1058460 see ecn kvm/ kkvtmp new data sheet
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